The present disclosure relates to electronic devices, more particularly, to a power-on reset circuit for integrated circuits used in electronic devices.
When the electric device is powered up, a supply voltage VDD of an electronic device rises from zero voltage to a pre-defined voltage (e.g. 3.3V). During this period, logic states of internal latches or flip-flops in the electronic device are un-known because they may carry logic memories from previous logic states. Un-known internal logic states can cause unpredictable behaviors in the electronic device and prevent the electronic device from performing its intended functions. A power-on-reset (POR) circuit can provide reset signals to reset internal latches or flip-flops to well-defined logic states during a power-on period, thus ensuring the proper functions of the electronic device.
A conventional POR circuit 100, as shown in FIG. 1, includes a Schmitt trigger circuit 110 consisting of transistors P12/P13/N12/N13, a stabilization capacitor CO, a current source PMOS transistor P11, a resistor divider consisting of resistors R1 and R2, and an NMOS transistor N1. An output signal can be produced at a node PORB for resetting internal logics in an electronic device. The PMOS transistor P11 can provide source current from VDD to the resistor divider. The NMOS transistor N1 can produce a trigger signal at the node S2 for the Schmitt trigger circuit 110. The Schmitt trigger circuit 110 can bypass voltage fluctuations and clamp the voltage of the output node PORB during powers up. The PORB node is initially at ground voltage (which can be defined as zero voltage).
During power on, VDD rises from ground voltage to a pre-defined voltage, say 3.3V. The gate node of PMOS transistor P11 and the gate node of PMOS transistor P12 are both at zero voltage, thus both turn on. The current flows through P11 can produce a voltage at the node S1 as defined by VIN×R2/(R1+R2) where VIN is the drain voltage of P11. The current flows through P12 can cause the voltage at S2 to follow the rise of the voltage supply VDD. The node S2 has a higher voltage than the node S1 as S1 is resistive divided by VDD.
NMOS transistor N13 can therefore turn on once the voltage at the node S2 reaches its threshold turn-on voltage. When N13 turns on, the node PORB is further clamped to zero voltage. When VDD rises up further to reach the threshold turn-on voltage of NMOS transistor N1, N1 is turned on and pulls the node S2 low. At that moment, P12 is already turned on and therefore P12/N1 forms a resistive divider at the node S2. If N1 is made much larger than P12, then the pulling effect to the node S2 is much stronger at N1, the node S2 can be easily pulled to zero voltage, which can shut off the N13 and turns on P13. As a result, the PORB node changes from logic low to logic high. Subsequently P12 is shut off and N12 is turned on by the high logic level at the node PORB. P11 is also shut off, thus preventing direct DC current from flowing through the resistive divider and minimizing power consumption.
Recently, more and more integrated circuits are powered by multiple power supplies that may have the same or different voltages. The logic portion of the integrated circuit may be supplied at 1.8 volt. The 10 portion of the integrated circuit may be powered at 3.3 volt. The analog portion of the integrated circuit may be supplied by yet another different power supply also at 3.3 volt.
Conventional POR circuits such as the POR circuit 100 cannot provide power-on reset functions to this type of integrated circuits because the single power supply involved. Additionally, conventional POR circuits such as the POR circuit 100 cannot properly handle power-on resets when the power supplies are turned on in different sequences.
There is therefore a need for a power-on-reset circuit to perform proper reset functions for integrated circuits supplied by different power sources.